SN74ALS992 9-bit d-type transparent read-back latch with 3-state outputs sdas028b april 1984 revised january 1995 copyright ? 1995, texas instruments incorporated 1 post office box 655303 ? dallas, texas 75265 ? 3-state i/o-type read-back inputs ? bus-structured pinout ? true logic outputs ? designed with nine bits for parity applications ? package options include plastic small-outline (dw) packages and standard plastic (nt) 300-mil dips description this 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. in addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications. the nine latches are transparent d-type latches. while the latch-enable (le) input is high, the q outputs follow the data (d) inputs. the q outputs are in the 3-state condition when the output-enable (oeq ) input is high. read back is provided through the output-enable (oerb ) input. when oerb is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. when oerb is taken high, the output of the data latches is isolated from the d inputs. oerb does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict. the SN74ALS992 is characterized for operation from 0 c to 70 c. logic symbol 2 c1 13 le 2d 3 3d 4 4d 5 5d 6 6d 7 7d 8 8d 9 2 5q 19 6q 18 7q 17 8q 16 2q 22 3q 21 4q 20 1q 23 1d 2 1d r 11 clr en2 1 oerb en3 14 oeq 3 9d 10 9q 15 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. dw or nt package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 oerb 1d 2d 3d 4d 5d 6d 7d 8d 9d clr gnd v cc 1q 2q 3q 4q 5q 6q 7q 8q 9q oeq le production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
SN74ALS992 9-bit d-type transparent read-back latch with 3-state outputs sdas028b april 1984 revised january 1995 2 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1d c1 to eight other channels 1 13 2 23 oerb le 1d 1q 14 oeq 11 clr r timing diagram data bus le oerb q t su t h t pd t dis input data read back input data t pd t su 2 clr = h, oeq = l 2 this setup time ensures that the read-back circuit will not create a conflict on the input data bus. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage, v cc 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i (oerb , oeq , clr , and le) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to d inputs and to disabled 3-state outputs 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN74ALS992 9-bit d-type transparent read-back latch with 3-state outputs sdas028b april 1984 revised january 1995 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions min nom max unit v cc supply voltage 4.5 5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v i oh high-level output current q 2.6 ma i oh hi g h - l eve l ou t pu t curren t d 0.4 m a i ol low-level output current q 24 ma i ol l ow- l eve l ou t pu t curren t d 8 m a t w pulse duration le high 10 ns t w p u l se d ura ti on clr low 10 ns t su setup time data before le 10 ns t su s e t up ti me data before oerb 10 ns t h hold time, data after le 5 ns t a operating free-air temperature 0 70 c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit v ik v cc = 4.5 v, i i = 18 ma 1.2 v v oh all outputs v cc = 4.5 v to 5.5 v, i oh = 0.4 ma v cc 2 v v oh q v cc = 4.5 v, i oh = 2.6 ma 2.4 3.2 v v d v cc =45v i ol = 4 ma 0.25 0.4 v v ol d v cc = 4 . 5 v i ol = 8 ma 0.35 0.5 v v ol q v cc =45v i ol = 12 ma 0.25 0.4 v q v cc = 4 . 5 v i ol = 24 ma 0.35 0.5 i ozh q v cc = 5.5 v, v o = 2.7 v 20 m a i ozl q v cc = 5.5 v, v o = 0.4 v 20 m a i i d inputs v cc =55v v i = 5.5 v 0.1 ma i i all others v cc = 5 . 5 v v i = 7 v 0.1 m a i ih d inputs 3 v cc =55v v i =27v 20 m a i ih all others v cc = 5 . 5 v , v i = 2 . 7 v 20 m a i il d inputs 3 v cc =55v v i =04v 0.1 ma i il all others v cc = 5 . 5 v , v i = 0 . 4 v 0.1 m a i o v cc = 5.5 v, v o = 2.25 v 30 112 ma i v cc =55v outputs high 30 50 a i cc v cc = 5.5 v, oerb hi g h outputs low 50 80 ma cc oerb high outputs disabled 35 55 2 all typical values are at v cc = 5 v, t a = 25 c. 3 for i/o ports (q a thru q h ), the parameters i ih and i il include the off-state output current. the output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, i os .
SN74ALS992 9-bit d-type transparent read-back latch with 3-state outputs sdas028b april 1984 revised january 1995 4 post office box 655303 ? dallas, texas 75265 switching characteristics (see figure 1) parameter from (input) to (output) v cc = 4.5 v to 5.5 v, c l = 50 pf, t a = min to max 2 unit () () min max t plh d q 3 14 ns t phl d q 4 16 ns t plh le q 6 20 ns t phl le q 8 25 ns t phl clr q 6 20 ns t phl clr d 8 26 ns t en 3 oerb d 4 21 ns t dis oerb d 2 14 ns t en 3 oeq q 4 18 ns t dis oeq q 1 14 ns 2 for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. 3 t en = t pzh or t pzl t dis = t phz or t plz
SN74ALS992 9-bit d-type transparent read-back latch with 3-state outputs sdas028b april 1984 revised january 1995 5 post office box 655303 ? dallas, texas 75265 parameter measurement information load circuit for q outputs from output under test test point 500 w s1 c l (see note a) 7 v 500 w load circuit for d outputs from output under test test point 1 k w s1 c l (see note a) 7 v 1 k w 1.3 v 1.3 v 1.3 v 3.5 v 3.5 v 0.3 v 0.3 v t h t su voltage waveforms setup and hold times timing input data input 1.3 v 1.3 v 3.5 v 3.5 v 0.3 v 0.3 v high-level pulse low-level pulse t w voltage waveforms pulse durations 1.3 v 1.3 v t phz t plz 0.3 v t pzl t pzh 1.3 v 1.3 v 1.3 v 1.3 v 3.5 v 0.3 v output control (low-level enabling) waveform 1 s1 closed (see note c) waveform 2 s1 open (see note c) 0 v v oh v ol 3.5 v 0.3 v voltage waveforms enable and disable times, 3-state outputs t phl t plh t plh t phl input out-of-phase output (see note b) 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 3.5 v 0.3 v v ol v oh v oh v ol in-phase output voltage waveforms propagation delay times notes: a. c l includes probe and jig capacitance. b. when measuring propagation delay times of 3-state outputs, switch s1 is open. c. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. d. all input pulses have the following characteristics: prr 1 mhz, t r = t f = 2 ns, duty cycle = 50%. figure 1. load circuits and voltage waveforms
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